Processor System Design: CPU interfaces, clock, control, data & address bus; System firmware. The CPU Architecture: including ISA, compiler relationship, control, pipelining, hazards, CISC/RISC/VLIW and issues of ILP. Memory Systems: cache, virtual memory systems and the MMU, access methods, reliability, error detection/correction. Performance Enhancements: superscalar; branching issues, multithreading, scalability, co-processors and enhancement units. Interfacing and Communications: I/O fundamentals, interrupts and interfacing, buses, protocols and arbitration. Computer Arithmetic: range, precision, real numbers, floating point and conversion, multi-precision arithmetic Multiprocessing: multiprocessing architectures and interconnections, shared memory and coherence, memory solutions Future directions: low power computing; testing, JTAG, system-on-chip and multi-core implementations, embedded systems issues, comparison of computational on CPU, DSP, FPGA and GPU.
| Academic Units | 3 |
| Exam Schedule | Mon May 04 2026 00:00:00 GMT+0000 (Coordinated Universal Time) 17:00-19:00 |
| Grade Type | Letter Graded |
| Department Maintaining | CSC(CE) |
| Prerequisites | |
| Mutually Exclusive | |
| Not Available to Programme | BCE, CE, CEEC |
| Not Available to All Programme | (Admyr 2021-onwards) |
| Not Available as PE to Programme | REP(ASEN), REP(BIE), REP(CBE), REP(CE), REP(CVEN), REP(EEE), REP(ENE), REP(MAT), REP(ME) |
| Index | Type | Group | Day | Time | Venue | Remark |
|---|
0930
1030
1130
1230
1330
1430
1530
1630
1730
We would encourage you to review with the following template.
AY Taken: ...
Assessment (Optional): ...
Topics (Optional): ...
Lecturer (Optional): ...
TA (Optional): ...
Review: ...
Final Grade (Optional): ...