Review of Hardware Description Languages; Real-World Arithmetic; Control and Datapath design; Register Transfer Level (RTL) design in Verilog; Digital Design on FPGAs; Testbenches and Testing Strategies; Using design in registers, counters, shift registers, synchronous and asynchronous reset
| Academic Units | 3 |
| Exam Schedule | Mon Apr 28 2025 00:00:00 GMT+0000 (Coordinated Universal Time) 09:00-11:00 |
| Grade Type | Letter Graded |
| Department Maintaining | CE |
| Prerequisites | |
| Mutually Exclusive | |
| Not Available to Programme | BCG, CEE 1, CSC, CSEC, EEE, EEE 1, EEEC, ENE 1, ENG, ME 1, ME(DES), ME(IMS), ME(NULL), ME(RMS), MEEC(DES), MEEC(NULL), MEEC(RMS) Not offered as Broadening and Deepening Elective |
| Index | Type | Group | Day | Time | Venue | Remark |
|---|
0930
1030
1130
1230
1330
1430
1530
1630
1730
We would encourage you to review with the following template.
AY Taken: ...
Assessment (Optional): ...
Topics (Optional): ...
Lecturer (Optional): ...
TA (Optional): ...
Review: ...
Final Grade (Optional): ...